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M5M5V5636UG - 16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DESCRIPTION
The M5M5V5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Renesas's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5V5636UG operates on 3.3V power/ 2.5V I/O supply or a single 3.3V power supply and are 3.3V CMOS compatible. The M5M5V5636UG also operates on a single 2.5V power supply and is also 2.5V CMOS compatible. Therefore the M5M5V5636UG can replace the M5M5T5636UG. The M5M5V5636UG-16 operates at 167MHz or 133MHz and is guaranteed both AC DC electrical characteristics of 167MHz and those of 133MHz.
PACKAGE 165(11x15) bump BGA Body Size (13mm x 15mm) Bump Pitch 1.0mm
APPLICATION
High-end networking products that require high bandwidth, such as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#, BWd#) and Read/Write (W#). Write operations are controlled by the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. Asynchronous inputs include Output Enable (G#), Clock (CLK) and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the SRAM in the power-down state.The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst. All read, write and deselect cycles are initiated by the ADV LOW input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input.
FEATURES
* Fully registered inputs and outputs for pipelined operation * Fast clock speed: 167 and 133 MHz * Fast access time: 3.8 and 4.2 ns * Single 3.3V -5% and +5% power supply VDD * Separate VDDQ for 3.3V or 2.5V I/O * Single 2.5V -5% and +5% power supply VDD * Individual byte write (BWa# - BWd#) controls may be tied LOW * Single Read/Write control pin (W#) * CKE# pin to enable clock and suspend operations * Internally self-timed, registers outputs eliminate the need to control G# * Snooze mode (ZZ) for power down * Linear or Interleaved Burst Modes * Three chip enables for simple depth expansion * JTAG boundary scan support
PART NAME TABLE M5M5V5636UG-16 Operate frequency Access Cycle Active Current (max.) Standby Current (max.)
167MHz 133MHz
3.8ns 4.2ns
6.0ns 7.5ns
380mA 350mA
30mA 30mA
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M5M5V5636UG - 16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
BUMP LAYOUT(TOP VIEW) 165bump-BGA
1 A B C D E F G H J K L M N P R 2 3 4 5 6 7 8 9 10 11
NC NC DQPc DQc DQc DQc DQc MCH DQd DQd DQd DQd DQPd NC LBO#
A7 A6 NC DQc DQc DQc DQc MCH DQd DQd DQd DQd NC NC NC
E1# E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A5 A4
BWc# BWd# VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A3 A2
BWb# BWa# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS
E3# CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
CKE# W# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MCH TDO TCK
ADV G# VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A15 A16
A17 A18 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A13 A14
A8 A9 NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A11 A12
NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A10
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
BLOCK DIAGRAM
VDD VDDQ
A0 A1 A2~18
19 19 ADDRESS REGISTER A1 D1 A0 D0 LINEAR/ INTERLEAVED BURST COUNTER Q1 A0' Q0 A1' 17
LBO# CLK CKE#
19
WRITE ADDRESS REGISTER1
WRITE ADDRESS REGISTER2
19
ZZ ADV BWa# BWb# BWc# BWd# W#
BYTE1 WRITE DRIVERS OUTPUT REGISTERS BYTE2 WRITE DRIVERS BYTE3 WRITE DRIVERS BYTE4 WRITE DRIVERS 256Kx36 OUTPUT BUFFERS
AND DATA COHERENCY CONTROL LOGIC
MEMORY ARRAY
INPUT 36 REGISTER1
INPUT REGISTER0
G# E1# E2 E3#
READ LOGIC
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter. Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION and timing diagrams for detailed information.
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OUTPUT SELECT
WRITE REGISTRY
DQa DQPa DQb DQPb DQc DQPc DQd DQPd
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN FUNCTION
Pin A0~A18
Name Synchronous Address Inputs Synchronous Byte Write Enables
Function
These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls DQc, DQPc pins; BWd# controls DQd, DQPd pins. This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This active High input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. This active Low input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. This active LOW asynchronous input enable the data I/O output drivers. When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. This active LOW input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. This active HIGH asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. When this pin is LOW or NC, the SRAM normally operates. This active input determines the cycle type when ADV is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. Byte "a" is DQa , DQPa pins; Byte "b" is DQb, DQPb pins; Byte "c" is DQc, DQPc pins; Byte "d" is DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge. This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input leak current to this pin. Core Power Supply Ground I/O buffer Power supply
BWa#, BWb#, BWc#, BWd#
CLK E1# E2 E3# G# ADV CKE# ZZ
Clock Input Synchronous Chip Enable Synchronous Chip Enable Synchronous Chip Enable Output Enable Synchronous Address Advance/Load Synchronous Clock Enable Snooze Enable
W#
Synchronous Read/Write
DQa,DQPa,DQb,DQPb DQc,DQPc,DQd,DQPd LBO# VDD VSS VDDQ TDI TDO TCK TMS MCH NC
Synchronous Data I/O Burst Mode Control VDD VSS VDDQ Test Data Input Test Data Output Test Clock Test Mode Select
Must Connect High
These pins are used for Boundary Scan Test.
These pins should be connected to HIGH These pins are not internally connected and may be connected to ground.
No Connect
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name Input Status Operation
LBO#
HIGH or NC LOW
Interleaved Burst Sequence Linear Burst Sequence
Note4. LBO# is DC operated pin. Note5. NC means No Connection. Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation A18~A2 A1,A0
First access, latch external address Second access(first burst address) Third access(second burst address) Fourth access(third burst address) Linear Burst Sequence (when LBO# = LOW)
Operation
A18~A2 latched A18~A2 latched A18~A2 latched A18~A2
0,0 0,1 1,0 1,1
0,1 0,0 1,1 1,0
1,0 1,1 0,0 0,1
1,1 1,0 0,1 0,0
A18~A2
A1,A0
First access, latch external address Second access(first burst address) Third access(second burst address) Fourth access(third burst address)
A18~A2 latched A18~A2 latched A18~A2 latched A18~A2
0,0 0,1 1,0 1,1
0,1 1,0 1,1 0,0
1,0 1,1 0,0 0,1
1,1 0,0 0,1 1,0
Note7. The burst sequence wraps around to its initial state upon completion.
TRUTH TABLE
E1# E2 E3# ZZ ADV W# BWx# G# CKE# CLK DQ Address used Operation
H X X X L X L X L X L X X
X L X X H X H X H X H X X
X X H X L X L X L X L X X
L L L L L L L L L L L L L
L L L H L H L H L H L H X
X X X X H X H X L X L X X
X X X X X X X X L L H H X
X X X X L L H H X X X X X
L L L L L L L L L L L L H
L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H L->H
High-Z High-Z High-Z High-Z Q Q High-Z High-Z D D High-Z High-Z -
None None None None External Next External Next External Next None Next Current
Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Dummy Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst NOP/Write Abort, Begin Burst Write Abort, Continue Burst Ignore Clock edge, Stall
X X X H X X X X X X High-Z None Snooze Mode Note8. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL. Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more Synchronous Byte Write Enables are LOW. Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5/25 M5M5V5636UG-16 REV.2.0
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
STATE DIAGRAM
F,L,X
Deselect
F,L,X
T,L,H
X,H,X
T,L,L
F,L,X
T,L,H
Read Begin Burst
T,L,L T,L,H
Write Begin Burst
T,L,L
T,L,H
X,H,X
X,H,X
T,L,L
X,H,X
Read Continue Burst
T,L,L
T,L,H
Write Continue Burst
X,H,X
Key
Input Command Code
f
Transition
Current State
Next State
Note11. The notation "x , x , x" controlling the state transitions above indicate the state of inputs E, ADV and W# respectively. Note12. If (E1# = L and E2 = H and E3# = L) then E="T" else E="F". Note13. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL; "T" = input "true"; "F" = input "false".
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
WRITE TRUTH TABLE
W# H L L L L L BWa# X L H H H L BWb# X H L H H L BWc# X H H L H L BWd# X H H H L L Function
L H H H H Note14. "H"=input VIH; "L"=input VIL; "X"=input VIH or VIL. Note15. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Power Supply Voltage I/O Buffer Power Supply Voltage Input Voltage Output Voltage Maximum Power Dissipation (VDD) Operating Temperature Storage Temperature(bias) With respect to VSS Conditions Ratings Unit V V V V W C C C
VDD VDDQ VI VO PD TOPR TSTG(bias) TSTG
Storage Temperature Note16.* This is -1.0V when pulse width2ns, and -0.5V in case of DC. ** This is -1.0V~VDDQ+1.0V when pulse width2ns, and -0.5V~VDDQ+0.5V in case of DC.
-1.0*~4.6 -1.0*~4.6 -1.0~VDDQ+1.0** -1.0~VDDQ+1.0** 1.6 0~70 -10~85 -55~125
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC ELECTRICAL CHARACTERISTICS1 (Ta=0~70C, VDD=3.135~3.465V, unless otherwise noted)
Limits Symbol Parameter Power Supply Voltage VDDQ = 3.3V I/O Buffer Power Supply Voltage VDDQ = 2.5V VDDQ = 3.135~3.465V High-level Input Voltage VDDQ = 2.375~2.625V VDDQ = 3.135~3.465V Low-level Input Voltage VDDQ = 2.375~2.625V High-level Output Voltage Low-level Output Voltage Input Leakage Current except ZZ and LBO# IOH = -2.0mA IOL = 2.0mA VI = 0V ~ VDDQ VI = 0V ~ VDDQ VI = 0V ~ VDDQ VI (G#) VIH, VO = 0V ~ VDDQ Device selected; Output Open VIVIL or VIVIH ZZVIL Device deselected VIVIL or VIVIH ZZVIL 6.0ns cycle(167MHz) 7.5ns cycle(133MHz) 6.0ns cycle(167MHz) 7.5ns cycle(133MHz) Condition Min Max Unit
VDD VDDQ
3.135 3.135 2.375 2.0 1.7 -0.3* VDDQ-0.4
3.465 3.465 2.625 VDDQ+0.3* 0.8 0.7
V V
VIH
V
VIL VOH VOL
V V
0.4 10 100 100 10 380
V
ILI
Input Leakage Current of LBO# Input Leakage Current of ZZ
A
ILO
Off-state Output Current
A
ICC1
Power Supply Current : Operating
mA
350 160 130 30 30 130
mA mA
ICC2
Power Supply Current : Deselected
Device deselected; Output Open VIVSS+0.2V or VIVDDQ-0.2V CLK frequency=0Hz, All inputs static Snooze mode ICC4 Snooze Mode Standby Current ZZVDDQ-0.2V, LBO#VDD-0.2V Device selected; 6.0ns cycle(167MHz) Output Open ICC5 Stall Current CKE#VIH VIVSS+0.2V or 7.5ns cycle(133MHz) VIVDDQ-0.2V Note17.*VILmin is -1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width2ns). Note18."Device Deselected" means device is in power-down mode as defined in the truth table.
ICC3
CMOS Standby Current (CLK stopped standby mode)
mA mA
120
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC ELECTRICAL CHARACTERISTICS 2 (Ta=0~70C, VDD=2.375~2.625V, unless otherwise noted)
Limits Symbol Parameter Power Supply Voltage I/O Buffer Power Supply Voltage High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input Leakage Current except ZZ and LBO# Input Leakage Current of LBO# Input Leakage Current of ZZ Off-state Output Current IOH = -2.0mA IOL = 2.0mA VI = 0V ~ VDDQ VI = 0V ~ VDDQ VI = 0V ~ VDDQ VI (G#) VIH, VO = 0V ~ VDDQ Device selected; Output Open, VIVIL or VIVIH, ZZVIL Device deselected VIVIL or VIVIH, ZZVIL 6.0ns cycle(167MHz) 7.5ns cycle(133MHz) 6.0ns cycle(167MHz) 7.5ns cycle(133MHz) Condition Min Max Unit
VDD VDDQ VIH VIL VOH VOL ILI
2.375 2.375 1.7 -0.3* VDDQ-0.4
2.625 2.625 VDDQ+0.3* 0.7 0.4 10 100 100 10 380
V V V V V V
A
ILO ICC1
A
Power Supply Current : Operating
mA
350 160
mA
ICC2
Power Supply Current : Deselected
130 30 30 130
mA mA mA
Device deselected; Output Open VIVSS+0.2V or VIVDDQ-0.2V CLK frequency=0Hz, All inputs static Snooze mode ICC4 Snooze Mode Standby Current ZZVDDQ-0.2V, LBO#VDD-0.2V Device selected; 6.0ns cycle(167MHz) Output Open, ICC5 Stall Current CKE#VIH VIVSS+0.2V or 7.5ns cycle(133MHz) VIVDDQ-0.2V Note17.*VILmin is -1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width2ns). Note18."Device Deselected" means device is in power-down mode as defined in the truth table.
ICC3
CMOS Standby Current (CLK stopped standby mode)
120
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
CAPACITANCE
Symbol Parameter Input Capacitance Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND, VO=25mVrms, f=1MHz Limits Min Typ Max Unit pF pF
CI CO
Input / Output(DQ) Capacitance Note19.This parameter is sampled.
6 8
THERMAL RESISTANCE 4-Layer PC board mounted (70x70x1.6mmT)
Symbol Parameter Thermal Resistance Junction Ambient Conditions Air velocity=0m/sec Air velocity=2m/sec Limits Min Typ Max Unit C/W C/W C/W
JA JC
Thermal Resistance Junction to Case Note20.This parameter is sampled.
28 20 4
AC ELECTRICAL CHARACTERISTICS (Ta=0~70C, VDD=3.135~3.465V or VDD=2.375~2.625V, unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels **************************************** VIH=VDDQ, VIL=0V Input rise and fall times ******************************* faster than or equal to 1V/ns Input timing reference levels *********************** VIH=VIL=0.5*VDDQ Output reference levels *******************************VIH=VIL=0.5*VDDQ Output load ************************************************** Fig.1
Q ZO=50 50 VT=0.5*VDDQ Fig.1 Output load
Input Waveform toff tplh Output Waveform VDDQ / 2 tphl Output Waveform Vh (toff) Vl VDDQ / 2 ton (ton)
30pF (Including wiring and JIG)
Input Waveform
VDDQ / 2
Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz)) Vz 0.2(Vz-Vl) Vz-(0.2(Vz-Vl))
Fig.2 Tdly measurement
Fig.3 Tri-State measurement
Note21.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform. Input waveform should have a slew rate of faster than or equal to 1V/ns. Note22.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial to final Value VDDQ/2. Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note23. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial Value VDDQ/2 to its final Value. Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note24.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns.
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(2)TIMING CHARACTERISTICS
Symbol Parameter Limits 167MHz 133MHz -16 -16 Min Max Min Max Unit
tKHKH tKHKL tKLKH tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX1 tGHQZ tAVKH tckeVKH tadvVKH tWVKH tBVKH tEVKH tDVKH tKHAX tKHckeX tKHadvX tKHWX tKHBX tKHEX tKHDX tZZS tZZREC
Clock cycle time Clock HIGH time Clock LOW time Clock HIGH to output valid Clock HIGH to output invalid Clock HIGH to output in LOW-Z Clock HIGH to output in High-Z G# to output valid G# to output in Low-Z G# to output in High-Z Address valid to clock HIGH CKE# valid to clock HIGH ADV valid to clock HIGH Write valid to clock HIGH Byte write valid to clock HIGH (BWa#~BWd#) Enable valid to clock HIGH (E1#,E2,E3#) Data In valid clock HIGH Clock HIGH to Address don't care Clock HIGH to CKE# don't care Clock HIGH to ADV don't care Clock HIGH to Write don't care Clock HIGH to Byte Write don't care (BWa#~BWb#) Clock HIGH to Enable don't care (E1#,E2,E3#) Clock HIGH to Data In don't care
6.0 2.7 2.7 3.8 1.5 1.5 1.5 0.0 3.8 1.2 1.2 1.2 1.2 1.2 1.2 1.2 0.8 0.8 0.8 0.8 0.8 0.8 0.8
7.5 3.0 3.0 4.2 1.5 1.5 1.5 0.0 4.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 0.8 0.8 0.8 0.8 0.8 0.8 0.8
2*tKHKH 2*tKHKH
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.8 3.8
4.2 4.2
ZZ standby 2*tKHKH ZZ recovery 2*tKHKH Note25.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix. Note26.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted. Note27. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled. Note28.LBO# is static and must not change during normal operation.
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(3)READ TIMING
tKHKH
CLK
tKHKL tckeVKH tKHckeX tKLKH
CKE#
tEVKH tKHEX
E#
tadvVKH tKHadvX
ADV
tWVKH tKHWX
W#
BWx#
tAVKH tKHAX
A1 A2 A3
ADD
tKHQX1
tGLQV
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A3) Q(A3+1)
DQ
tKHQV
tKHQX
tGHQZ tGLQX1
tKHQZ
G#
Read A1 Read A2 Burst Read A2+1 Stall Burst Read Burst Read Burst Read A2+2 A2+3 A2 Deselect Continue Deselect Read A3 Burst Read Burst Read Burst Read A3+1 A3+2 A3+3
DON'T CARE
UNDEFINED
Note29.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note30. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note31.ZZ is fixed LOW.
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(4)WRITE TIMING
tKHKH
CLK
tKHKL tckeVKH tKHckeX tKLKH
CKE#
tEVKH tKHEX
E#
tadvVKH tKHadvX
ADV
tWVKH tKHWX
W#
tBVKH tKHBX
BWx#
tAVKH tKHAX
A1 A2 A3 A4
ADD
tDVKH tKHDX
DQ
D(A1)
D(A2)
D(A2+1)
D(A2+3)
D(A2)
D(A3)
D(A4)
D(A4+1)
G#
Write A1 Write A2 Burst Write A2+1 NOP Burst Write A2+3 Write A2 Write A3 NOP Write A4 Burst Write A4+1 Stall Burst Write Burst Write A4+2 A4+3
DON'T CARE
UNDEFINED
Note32.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note33. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note34.ZZ is fixed LOW.
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(5)READ/WRITE TIMING
tKHKH
CLK
tKHKL tckeVKH tKHckeX tKLKH
CKE#
tEVKH tKHEX
E#
tadvVKH tKHadvX
ADV
tWVKH tKHWX
W#
tBVKH tKHBX
BWx#
tAVKH tKHAX
A1 A2 A2 A3 A3 A4 A5
ADD
tKHQX1
tDVKH tKHDX
Q(A1) D(A2) Q(A2) D(A3) D(A3+1) Q(A3) Q(A3+1) D(A4) Q(A5)
DQ
tKHQV
tKHQV
G#
Read A1 Write A2 Read A2 Write A3 Burst Write A3+1 Read A3 Burst Read A3+1 Deselect Write A4 Stall Read A5 Burst Read Burst Read A5+1 A5+2
DON'T CARE
UNDEFINED
Note35.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note36. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note37.ZZ is fixed LOW.
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
(6)SNOOZE MODE TIMING
CLK
tZZS tZZREC
ZZ
All Inputs (except ZZ)
DESELECT or READ only
Q
Snooze Mode
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
JTAG PORT OPERATION Overview
The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. The JTAG Port interfaces with conventional CMOS logic level signaling.
Disabling the JTAG port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The TDO pin should be left unconnected.
JTAG Pin Description
Test Clock (TCK) The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates from the falling edge of TCK. Test Mode Select (TMS) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven TMS input will produce the same result as a logic one input level. Test Data In (TDI) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins. the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce the same result as a logic one input level. Test Data Out (TDO) The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between the TDI and TDO pins. Note: This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and 0s applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM Bypass Register The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the Capture-RD state and then is placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instruction can be used to activate the Boundary Scan Register. Identification (ID) Register The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the Capture-DR state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It describes various attributes of the SRAM (see page 20). The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins.
TAP Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private) instructions. Some public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP Controller in this device is not fully 1194.1-compliant because some of the mandatory 1149.1 instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads. This device will not perform INTEST or PRELOAD portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction Set for this device is listed in the following table. Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the Boundary Scan Register. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for long enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the Shift-DR state then places the Boundary Scan Register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This functionality is not Standard 1149.1 compliant. 17/25 M5M5V5636UG-16 REV.2.0
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the Instruction Register is loaded with all logic 0s. EXTEST is not implemented in the TAP Controller, and therefore this device is not compliant to the 1149.1 Standard. When the EXTEST instruction is loaded into the Instruction Register, the device responds as if the SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST place the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction cause the ID ROM to be loaded into the ID register when the controller is in the Capture-DR state and places the ID Register between the TDI and TDO pins in the Shift-DR state. The IDCODE instruction is the default instruction loaded in at power-up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the Instruction Register, all SRAM outputs are forced to an inactive drive state (High-Z) and the Boundary Scan Register is placed between the TDI and TDO pins when the TAP Controller is moved to the Shift-DR state. RFU These instructions are reserved for future use. Do not use these instructions.
JTAG TAP BLOCK DIAGRAM
Bypass Register 0 Instruction Register 210 TDI Identification Register 31 30 29 . . . . . . . . 2 1 0 Boundary Scan Register .. .............. .. 2 1 0 TDO
TMS TCK Test Access Port (TAP) Controller
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
BOUNDARY SCAN ORDER Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Bump 8P 8R 9P 9R 10P 10R 11R 11N 11M 10M 10L 11L 10K 11K 10J 11J 11H 7N 11G 10G 11F 10F 11E 10E 11D 10D 11C Pin Name A15 A16 A13 A14 A11 A12 A10 DQPa DQa DQa DQa DQa DQa DQa DQa DQa ZZ MCH DQb DQb DQb DQb DQb DQb DQb DQb DQPb Bit 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Bump 10A 10B 9A 9B 8A 8B 7A 7B 6B 6A 5B 5A 4A 4B 3B 3A 2A 2B 1C 1D 2D 1E 2E 1F 2F 1G 2G Pin Name A8 A9 A17 A18 ADV G# CKE# W# CLK E3# Bwa# BWb# BWc# BWd# E2 E1# A7 A6 DQPc DQc DQc DQc DQc DQc DQc DQc DQc Bit 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Bump 1H 2H 2J 1J 2K 1K 1L 2L 1M 2M 1N 1R 3R 3P 4R 4P 6P 6R Pin Name MCH MCH DQd DQd DQd DQd DQd DQd DQd DQd DQPd LBO# A4 A5 A2 A3 A1 A0
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
JTAG TAP CONTROLLER STATE DIAGRAM
Test-Logic-Reset 1 0 Run-Test/Idle 0 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 Exit2-DR 1 Update-DR 1 0 0 0 1 1 1 Select-IR-Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1
0
0
TAP CONTROLLER DC ELECTRICAL CHARACTERISTICS1 (Ta=0~70C, VDD=3.135~3.465V, unless otherwise noted)
Limits Min Max VIHT Test Port Input High Voltage 2.0 VDDQ+0.3 ** VILT Test Port Input Low Voltage -0.3 ** 0.8 VOHT Test Port Output High Voltage IOH=-100A VDDQ-0.1 VOLT Test Port Output Low Voltage IOL=+100A 0.1 TMS, TCK and TDI Input Leakage Current -10 10 IINT IOLT TDO Output Leakage Current Output Disable, VOUT=0V~VDDQ -10 10 Note38. **Input Undershoot/Overshoot voltage must be -1.0VTAP CONTROLLER DC ELECTRICAL CHARACTERISTICS2 (Ta=0~70C, VDD=2.375~2.625V, unless otherwise noted)
Limits Min Max VIHT Test Port Input High Voltage 1.7 VDDQ+0.3 ** VILT Test Port Input Low Voltage -0.3 ** 0.7 VOHT Test Port Output High Voltage IOH=-100A VDDQ-0.1 Test Port Output Low Voltage IOL=+100A 0.1 VOLT IINT TMS, TCK and TDI Input Leakage Current -10 10 IOLT TDO Output Leakage Current Output Disable, VOUT=0V~VDDQ -10 10 Note38. **Input Undershoot/Overshoot voltage must be -1.0VM5M5V5636UG-16 REV.2.0 Unit V V V V A A
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TAP CONTROLLER AC ELECTRICAL CHARACTERISTICS (Ta=0~70C, VDD=3.135~3.465V or VDD=2.375~2.625V, unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels **************************************** VIH=VDDQ, VIL=0V Input rise and fall times ******************************* faster than or equal to 1V/ns Input timing reference levels *********************** VIH=VIL=0.5*VDDQ Output reference levels *******************************VIH=VIL=0.5*VDDQ Output load ************************************************** Fig.4
Q ZO=50 50 VT=0.5*VDDQ Fig.4 Output load 30pF (Including wiring and JIG)
(2)TIMING CHARACTERISTICS
Symbol Parameter TCK Frequency TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TDI, TMS setup time TDI, TMS hold time TCK Low to TDO valid Limits Min Max 20 50 20 20 10 10 20 Unit MHz ns ns ns ns ns ns
tTF tTKC tTKH tTKL tTS tTH tTKQ
(3) TIMING
tTKC tTKH tTKL
TCK
tTS tTH
TMS
tTS tTH
TDI
tTKQ
TDO
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
JTAG TAP INSTRUCTION SET SUMMARY
Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/PRELOAD RFU RFU BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Preloads ID Register and places it between TDI and TDO Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all Data output drivers to High-Z Do not use this instruction; Reserved for Future Use. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. This instruction dose not implement 1149.1 preload function and is therefore not 1149.1-compliant. Do not use this instruction; Reserved for Future Use. Do not use this instruction; Reserved for Future Use. Places the BYPASS Register between TDI and TDO.
STRUCTURE OF IDENTIFICATION REGISTER
Revision Bit No.
M5M5V5636
31 30 29 28 27 26 25 24 23
Device Information
22 21 20 19 18 17 16 15 14 13 12 11
JEDEC Vendor Code of RENESAS
10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
MSB
LSB
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PACKAGE OUTLINE 165(11x15) bump Ball Grid Array(BGA) Pin Pitch 1.00mm
Refer to JEDEC Standard MO-216, Variation CAB-1, which can be seen at: http://www.jedec.org/download/search/MO-216c.pdf
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
REVISION HISTORY Rev. No. History The semiconductor operations of HITACHI and MITSUBISHI Electric were transferred to RENESAS Technology Corporation on April 1st 2003. Both RENESAS and MITSUBISHI JEDEC vendor code are as follows Bit No. 11 10 9 8 7 6 5 4 3 2 1 RENESAS 0 1000100011 MITSUBISHI 0 0000011100 Eliminate preliminary Be guaranteed 2.5V operation Eliminate M5M5V5636UG-13 Changed PD(Maximum Power Dissipation) from 1180mW to 1.6W Date
1.0
August 1, 2003
Preliminary
2.0
March31, 2004
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18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Nippon Bldg.,6-2,Oteamchi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
Keep safety first in your circuit designs!
* Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. * Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. * All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). * When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. * Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. * The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. * If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. * Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
REJ03C0075 (c) 2003 Renesas Technology Corp. New publication, effective March 2004. Specifications subject to change without notice.

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